arch/arm32/memory_access

This module provides implements architecture-independent load and store relations for ARM.

LDR and STR instructions can have their operands encoded several different ways, depending on which form of the instruction it is:

Op1 Op2 Op3 Op4

  1. Indirect Rt

  2. Indirect #offset Rt

  3. Indirect Rm Rt

  4. Rt2 Indirect Rt

  5. Rt2 Indirect #offset Rt

  6. Rt2 Indirect Rm Rt

Each is used for the following forms: (1)

LDR{type}{cond} Rt, [Rn {, #offset}] LDR{type}{cond} Rt, [Rn, #offset]! LDR{type}{cond} Rt, [Rn, ±Rm {, shift}] LDR{type}{cond} Rt, [Rn, ±Rm {, shift}]! LDR Rt, label -> treated as LDR Rt, [PC, #offset]

  1. LDR{type}{cond} Rt, [Rn], #offset

  2. LDR{type}{cond} Rt, [Rn], ±Rm {, shift}

  3. LDRD{cond} Rt, Rt2, [Rn {, #offset}] LDRD{cond} Rt, Rt2, [Rn, #offset]! LDRD{cond} Rt, Rt2, [Rn, ±Rm] LDRD{cond} Rt, Rt2, [Rn, ±Rm]! LDRD Rt, Rt2, label -> treated as LDR Rt, Rt2, [PC, #offset]

  4. LDRD{cond} Rt, Rt2, [Rn], #offset

  5. LDRD{cond} Rt, Rt2, [Rn], ±Rm

aggregated_access_operation(OperationPrefix:symbol, AccessType:symbol)

Build operation substrings for aggregated access types.

Previously, we used regex “match” functor with “VLD[1-4].*” and “VST[1-4].*”. However, it was very slow. When this Souffle PR is merged, we can evaluate that again.

https://github.com/souffle-lang/souffle/pull/2328

non_mult_shift_type(Type:symbol)

Shift types that cannot be represented as multiplication

non_mult_shift(EA:address, Op:operand_code)

At EA, an indirect operand Op has a shift that cannot be represented as multiplication.